EVAL-AD7960FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7960FMCZ' PDF : 24 Pages View PDF
AD7960
Data Sheet
Self Clocked Mode
The digital operation of the AD7960 in self clocked interface
mode is shown in Figure 36. This interface mode reduces the
number of traces between the ADC and the digital host to two
LVDS pairs (CLK± and D±) or to a single pair if sharing a
common CLK±. Multiple AD7960 devices can share a common
CLK± signal. This can be useful in reducing the number of
LVDS connections to the digital host.
When the self clocked interface mode is used, each ADC
data-word is preceded by a 010 header sequence. After tMSB has
elapsed, the first bit of the header, 0, automatically appears on
D±, and the remaining two bits of the header, 10, are then
clocked out by the first two CLK± falling edges at the beginning
of the next sample. This header (010) is used to synchronize D±
of each conversion in the digital host because, in this mode,
there is no clock output synchronous to the data (D±) to allow
the digital host to acquire the data output.
Synchronization of the D± data to the acquisition clock of the
digital host is accomplished by using one state machine per
AD7960 device. For example, using a state machine that runs at
the same speed as CLK± incorporates three phases of this clock
frequency (120° apart). Each phase acquires the D± data as
output by the ADC.
The AD7960 data captured on each phase of the state machine
clock is then compared. The location of the 1 in the header in
each set of acquired data allows the user to choose the state
machine clock phase that occurs during the data valid
window of D±.
The self clocked mode data capture method allows the digital
host to adapt its result capture timing to accommodate varia-
tions in propagation delay through any AD7960, for example,
where data is captured from multiple AD7960 devices sharing
a common input clock.
Conversions are initiated by a CNV± pulse. The CNV± pulse
must be returned low (tCNVH maximum) for valid operation.
After a conversion begins, it continues until completion.
Additional CNV± pulses are ignored during the conversion
phase. After the time, tMSB, elapses, the host begins to burst
the CLK± signal to the AD7960. All 20 CLK± pulses must be
applied in the window of time framed by tMSB and the
subsequent tCLKL. The required 20 CLK± pulses must finish
before tCLKL (referenced to the next conversion phase) elapses.
Otherwise, the data is lost because it is overwritten by the next
conversion result.
Set CLK± to idle high between bursts of 20 CLK± pulses. The
header bit and conversion data of the next ADC result are
output on subsequent falling edges of CLK± during the next
burst of the CLK± signal.
When the self clocked interface mode is used, the AD7960 also
allows the user to provide an extra (21st) clock pulse to see a
guaranteed 0 state at the end of the frame, as shown in Figure 37.
After tMSB has elapsed, the first bit of the header sequence, 0,
automatically appears on D± and the remaining two bits of the
header, 10, are then clocked out by the first two CLK± falling
edges at the beginning of the next sample. This header (010) is
used to synchronize D± of each conversion in the digital host
because, in this mode, there is no clock output synchronous to
the data (D±) to allow the digital host to acquire the data output.
SAMPLE N
tCNVH
tCYC
SAMPLE N + 1
CNV–
CNV+
tACQ
ACQUISITION
CLK–
CLK+
tCLKD
D+
D–
tCLK
19 20
ACQUISITION
tCLKL
1
2
3
4
19 20
ACQUISITION
1
2
tMSB
D1
N–1
D0
N–1
1
D17 D16
N
N
D1
D0
N
N
1
Figure 36. Self Clocked Interface Mode Timing Diagram
3
D17
N+1
Rev. C | Page 20 of 24
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