EVAL-ADV7393EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7393EBZ' PDF : 108 Pages View PDF
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to
Bit Number1
SR0 Register Bit Description
7 6 5 4 3 2 1 0 Register Setting
0x02 Mode
Reserved
Register 0 HD interlace external VSYNC
and HSYNC
0
0
1
Zero must be written to this bit.
Default.
If using HD HSYNC/VSYNCinterlace mode,
setting this bit to 1 is recommended (see the
HD Interlace External HSYNC and VSYNC
Considerations section for more information).
Test pattern black bar4
0
Disabled.
1
Enabled.
Manual CSC matrix adjust
0
Disable manual CSC matrix adjust.
1
Enable manual CSC matrix adjust.
Sync on RGB
0
No sync.
1
Sync on all RGB outputs.
RGB/YPrPb output select
0
RGB component outputs.
1
YPrPb component outputs.
SD sync output enable
0
No sync output.
1
Output SD syncs on HSYNC and VSYNC pins.
ED/HD sync output enable 0
No sync output.
1
Output ED/HD syncs on HSYNC and
VSYNC pins.
0x03
ED/HD
CSC
Matrix 0
x x LSBs for GY.
0x04
ED/HD
CSC
Matrix 1
x
xx
xx
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
xx
LSBs for GU.
0x05
ED/HD
CSC
Matrix 2
x x x x x x x x Bits[9:2] for GY.
0x06
ED/HD
CSC
Matrix 3
x x x x x x x x Bits[9:2] for GU.
0x07
ED/HD
CSC
Matrix 4
x x x x x x x x Bits[9:2] for GV.
0x08
ED/HD
CSC
Matrix 5
x x x x x x x x Bits[9:2] for BU.
0x09
ED/HD
CSC
Matrix 6
x x x x x x x x Bits[9:2] for RV.
1 x = Logic 0 or Logic 1.
2 ED = enhanced definition = 525p and 625p.
3 Available on the ADV7392/ADV7393 (40-pin devices) only.
4 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Reset
Value
0x20
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
Rev. G | Page 29 of 108
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