EVAL-ADV7393EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7393EBZ' PDF : 108 Pages View PDF
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Table 20. Register 0x30
SR7 to
SR0 Register
Bit Description
0x30
ED/HD Mode ED/HD output standard
Register 1
ED/HD input
synchronization format
ED/HD standard2
Bit Number
7 6 5 4 3 2 1 0 Register Setting
Note
0 0 EIA-770.2 output
ED
EIA-770.3 output
HD
0 1 EIA-770.1 output
1 0 Output levels for full
input range
1 1 Reserved
0
External HSYNC, VSYNC
and field inputs1
1
Embedded EAV/SAV
codes
00000
SMPTE 293M, ITU-BT.1358 525p at 59.94 Hz
00010
BTA-1004, ITU-BT.1362 525p at 59.94 Hz
00011
ITU-BT.1358
625p at 50 Hz
00100
ITU-BT.1362
625p at 50 Hz
00101
SMPTE 296M-1,
SMPTE 274M-2
720p at
60 Hz/59.94 Hz
00110
SMPTE 296M-3
720p at 50 Hz
00111
SMPTE 296M-4,
SMPTE 274M-5
720p at
30 Hz/29.97 Hz
01000
SMPTE 296M-6
720p at 25 Hz
01001
SMPTE 296M-7,
SMPTE 296M-8
720p at
24 Hz/23.98 Hz
01010
SMPTE 240M
1035i at
60 Hz/59.94 Hz
01011
Reserved
01100
Reserved
01101
SMPTE 274M-4,
SMPTE 274M-5
1080i at
30 Hz/29.97 Hz
01110
SMPTE 274M-6
1080i at 25 Hz
01111
SMPTE 274M-7,
SMPTE 274M-8
1080p at
30 Hz/29.97 Hz
10000
SMPTE 274M-9
1080p at 25 Hz
10001
SMPTE 274M-10,
SMPTE 274M-11
1080p at
24 Hz/23.98 Hz
10010
ITU-R BT.709-5
1080Psf at 24 Hz
10011 to 11111
Reserved
1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
2 See the HD Interlace External HSYNC and VSYNC Considerations section for more information.
Reset
Value
0x00
Rev. G | Page 31 of 108
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