Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Table 22. Register 0x34 to Register 0x38
SR7 to
SR0
0x34
Register
ED/HD Mode
Register 5
Bit Description
ED/HD timing reset
ED/HD HSYNC control2
ED/HD VSYNC control2
Reserved
ED Macrovision® enable3
0x35
ED/HD Mode
Register 6
Reserved
ED/HD VSYNC input/field
input
ED/HD horizontal/vertical
counter mode4
Reserved
Reserved
ED/HD sync on PrPb
ED/HD color DAC swap
0x36
0x37
0x38
ED/HD Y level5
ED/HD Cr level5
ED/HD Cb level5
ED/HD gamma correction
curve select
ED/HD gamma correction
enable
ED/HD adaptive filter
mode
ED/HD adaptive filter
enable
ED/HD Test Pattern Y level
ED/HD Test Pattern Cr level
ED/HD Test Pattern Cb level
Bit Number1
Reset
7 6 5 4 3 2 1 0 Register Setting
Value
0 Internal ED/HD timing counters enabled. 0x48
1 Resets the internal ED/HD timing counters.
0
HSYNC output control (see Table 55).
1
0
VSYNC output control (see Table 56).
1
1
0
ED Macrovision disabled.
1
ED Macrovision enabled.
0
0 must be written to this bit.
0
0 = Field input.
1
1 = VSYNC input.
0
Update field/line counter.
1
Field/line counter free running.
0
0
0
Disabled.
1
Enabled.
0
DAC 2 = Pb, DAC 3 = Pr
1
DAC 2 = Pr, DAC 3 = Pb.
0
Gamma Correction Curve A.
1
Gamma Correction Curve B.
0
Disabled.
1
Enabled.
0
Mode A.
1
Mode B.
0
Disabled.
1
Enabled.
x x x x x x x x Y level value.
x x x x x x x x Cr level value.
x x x x x x x x Cb level value.
0x00
0xA0
0x80
0x80
1 x = Logic 0 or Logic 1.
2 Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3 Applies to the ADV7390 and ADV7392 only.
4 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev. G | Page 33 of 108