EVAL-ADV7393EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7393EBZ' PDF : 108 Pages View PDF
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Table 29. Register 0x88 to Register 0x89
SR7 to
Bit Number
Reset
SR0 Register
Bit Description
7 6 5 4 3 2 1 0 Register Setting
Value
0x88 SD Mode Register 7 Reserved
0
0x00
SD noninterlaced mode
0
Disabled.
1
Enabled.
SD double buffering
0
Disabled.
1
Enabled.
SD input format
00
8-bit YCbCr input.
01
16-bit YCbCr input.1
10
10-bit YCbCr/16-bit SD RGB
input.1
11
Reserved.
SD digital noise reduction
0
Disabled.
1
Enabled.
SD gamma correction enable
0
Disabled.
1
Enabled.
SD gamma correction curve select 0
Gamma Correction Curve A.
1
Gamma Correction Curve B.
0x89 SD Mode Register 8 SD undershoot limiter
0 0 Disabled.
0x00
0 1 −11 IRE.
1 0 −6 IRE.
1 1 −1.5 IRE.
Reserved
0
0 must be written to this bit.
Reserved
0
Reserved.
SD chroma delay
00
Disabled.
01
4 clock cycles.
10
8 clock cycles.
11
Reserved.
Reserved
00
0 must be written to these bits.
1 Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 30. Register 0x8A to Register 0x98
SR7 to
SR0 Register
Bit Description
0x8A SD Timing Register 0 SD slave/master mode
SD timing mode
Reserved
SD luma delay
SD minimum luma value
SD timing reset
Bit Number1
Reset
7 6 5 4 3 2 1 0 Register Setting
Value
0 Slave mode.
0x08
1 Master mode.
00
Mode 0.
01
Mode 1.
10
Mode 2.
11
Mode 3.
1
00
No delay.
01
Two clock cycles.
10
Four clock cycles.
11
Six clock cycles.
0
−40 IRE.
1
−7.5 IRE.
x
A low-high-low transition
resets the internal SD
timing counters.
Rev. G | Page 40 of 108
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