EVAL-ADV7393EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7393EBZ' PDF : 108 Pages View PDF
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Table 19. Register 0x0B to Register 0x17
SR7 to
SR0 Register
Bit Description
0x0B
DAC 1, DAC 2,
DAC 3 output
levels
Positive gain to DAC output voltage
Negative gain to DAC output voltage
0x0D DAC power
mode
DAC 1 low power mode
DAC 2 low power mode
DAC 3 low power mode
SD/ED oversample rate select
0x10
Reserved
Cable detection DAC 1 cable detect
Read only
DAC 2 cable detect
Read only
Reserved
Unconnected DAC autopower-down
0x13
0x14
0x16
0x17
Pixel Port
Readback A2
Pixel Port
Readback B2
Control port
readback2
Software reset
Reserved
P[7:0] readback (ADV7390/ADV7391)
P[15:8] readback (ADV7392/ADV7393)
P[7:0] readback (ADV7392/ADV7393)
Reserved
VSYNC readback
HSYNC readback
SFL readback
Reserved
Reserved
Software reset
Reserved.
Bit Number1
Reset
7 6 5 4 3 2 1 0 Register Setting
Value
0 0 0 0 0 0 0 0 0%.
0x00
0 0 0 0 0 0 0 1 +0.018%.
0 0 0 0 0 0 1 0 +0.036%.
………………………
0 0 1 1 1 1 1 1 +7.382%.
0 1 0 0 0 0 0 0 +7.5%.
1 1 0 0 0 0 0 0 −7.5%.
1 1 0 0 0 0 0 1 −7.382%.
1 0 0 0 0 0 1 0 −7.364%.
………………………
1 1 1 1 1 1 1 1 −0.018%.
0 DAC 1 low power
disabled.
0x00
1 DAC 1 low power enabled.
0
DAC 2 low power
disabled.
1
DAC 2 low power enabled.
0
DAC 3 low power
disabled.
1
DAC 3 low power enabled.
0
SD = 16×, ED = 8×.
1
SD = 8×, ED = 4×.
0000
0 Cable detected on
DAC 1.
0x00
1 DAC 1 unconnected.
0
Cable detected on
DAC 2.
1
DAC 2 unconnected.
00
0
DAC autopower-down
disable.
1
DAC autopower-down
enable.
000
x x x x x x x x Read only.
0xXX
x x x x x x x x Read only.
x x x Read only.
x
x
x
xx
0
0
Writing a 1 resets the
1
device; this is a self-
clearing bit.
000000
0xXX
0xXX
0x00
1 x = Logic 0 or Logic 1.
2 For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
Rev. G | Page 30 of 108
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