EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 80 Pages View PDF
Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ADAS1000-1 Only
AVDD = 3.3 V ± 5%, IOVDD = 1.65 V to 3.6 V, AGND = DGND = 0 V, REFIN tied to REFOUT, externally supplied crystal/clock =
8.192 MHz. TA = −40°C to +85°C, unless otherwise noted. Typical specifications are mean values at TA = 25°C. The following timing
specifications apply for the master interface when ECGCTL register is configured for high performance mode (ECGCTL[3] = 1), see
Table 28.
Table 6.
Parameter1
Output Frame Rate2
fSCLK2
tMCSSA
tMDO
tMCSHD
tMCSW
Min Typ
128
2.5 × crystal
frequency
24.4
0
48.8
2173
2026
Max Unit Description
kHz All five 16-bit ECG data-words are available at frame rate of 128 kHz only
MHz Crystal frequency = 8.192 MHz
ns MCS valid setup time
ns MSCLK rising edge to MSDO valid delay
ns MCS valid hold time from MSCLK falling edge
ns MCS high time, SPIFW = 0, MCS asserted for entire frame as shown in
Figure 5, and configured in Table 33
ns MCS high time, SPIFW = 1, MCS asserted for each word in frame as shown in
Figure 6 and configured in Table 33
1 Guaranteed by characterization, not production tested.
2 Guaranteed by design, not production tested.
MSCLK
tMSCLK
tMSCLK
2
MCS
SPIFW = 0*
tMCSSA
tMCSHD
tMCSW
MSDO
MSB
D0_15
D0_14
D0_1
tMDO
LSB
D0_0
MSB
D1_15
D1_14
LSB
D5_0
MSB
D6_15
D6_14
LSB
D6_0
HEADER: 0xF AND 12-BIT COUNTER
5 × 16-BIT ECG DATA
16-BIT CRC WORD
*SPIFW = 0 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1/2 MSCLK CYCLE BETWEEN EACH WORD.
Figure 5. Data Read and Write Timing Diagram for SPIFW = 0, Showing Entire Packet of Data (Header, 5 ECG Words, and CRC Word)
tMSCLK
MSCLK
MCS
SPIFW = 1*
tMCSSA
tMSCLK
tMCSHD
tMCSW
MSB
LSB
MSB
LSB
MSB
LSB
MSDO
D0_15
D0_14
D0_1
tMDO
D0_0
D1_15
D1_14
D5_0
D6_15
D6_14
D6_0
HEADER: 0xF AND 12-BIT COUNTER
5 × 16-BIT ECG DATA
16-BIT CRC WORD
*SPIFW = 1 PROVIDES MCS FOR EACH FRAME, SCLK STAYS HIGH FOR 1 MSCLK CYCLE BETWEEN EACH WORD.
Figure 6. Data Read and Write Timing Diagram for SPIFW = 1, Showing Entire Packet of Data (Header, 5 ECG Words, and CRC Word)
Rev. C | Page 13 of 85
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