EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 80 Pages View PDF
ADAS1000/ADAS1000-1/ADAS1000-2
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC 1
AGND 2
NC 3
NC 4
NC 5
NC 6
REFGND 7
REFOUT 8
REFIN 9
ECG1 10
ECG2 11
ECG3 12
ECG4 13
ECG5 14
AGND 15
NC 16
PIN 1
ADAS1000-2
64-LEAD LQFP
TOP VIEW
(Not to Scale)
48 NC
47 DGND
46 IOVDD
45 SDO
44 SCLK
43 SDI
42 DRDY
41 CS
40 DGND
39 GPIO3
38 GPIO2
37 GPIO1
36 GPIO0
35 IOVDD
34 DGND
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND 1
ECG5 2
ECG4 3
ECG3 4
ECG2 5
ECG1 6
REFIN 7
REFOUT 8
REFGND 9
NC 10
NC 11
NC 12
NC 13
AGND 14
PIN 1
INDICATOR
ADAS1000-2
56-LEAD LFCSP
TOP VIEW
(Not to Scale)
42 DGND
41 IOVDD
40 GPIO0
39 GPIO1
38 GPIO2
37 GPIO3
36 DGND
35 CS
34 DRDY
33 SDI
32 SCLK
31 SDO
30 IOVDD
29 DGND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 10. ADAS1000-2 Companion 64-Lead LQFP Pin Configuration
NOTES
1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE;
IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 11. ADAS1000-2 Companion 56-Lead LFCSP Pin Configuration
Table 9. Pin Function Descriptions
ADAS1000
ADAS1000-1
ADAS1000-2
LQFP LFCSP LFCSP
LQFP LFCSP
18, 23, 15, 20,
58, 63 51, 56
15, 20, 51, 56
18, 23, 15, 20,
58, 63 51, 56
35, 46 30, 41 30, 41
35, 46 30, 41
Mnemonic
AVDD
IOVDD
26, 55 23, 48 23, 48
26, 55 23, 48
ADCVDD
30, 51 27, 44 27, 44
30, 51 27, 44
DVDD
2, 15,
24, 25,
56, 57
31, 34,
40, 47,
50
59
1, 14,
21, 22,
49, 50
28, 29,
36, 42,
43
19
1, 14, 21, 22,
49, 50
28, 29, 36, 42,
43
19
2, 15,
24, 25,
56, 57
31, 34,
40, 47,
50
59
1, 14, 21,
22, 49,
50
28, 29,
36, 42,
43
19
AGND
DGND
VREG_EN
10
6
6
11
5
5
12
4
4
13
3
3
14
2
2
ECG1_LA
ECG2_LL
ECG3_RA
ECG4_V1
ECG5_V2
Description
Analog Supply. See recommendations for bypass capacitors in the Power
Supply, Grounding, and Decoupling Strategy section.
Digital Supply for Digital Input/Output Voltage Levels. See recommendations
for bypass capacitors in the Power Supply, Grounding, and Decoupling
Strategy section.
Analog Supply for ADC. There is an on-chip linear regulator providing the
supply voltage for the ADCs. This pin is primarily provided for decoupling
purposes; however, the pin may also be supplied by an external 1.8 V supply if
the user wants to use a more efficient supply to minimize power dissipation.
In this case, use the VREG_EN pin tied to ground to disable the ADCVDD
and DVDD regulators. Do not use the ADCVDD to supply other functions.
See recommendations for bypass capacitors in the Power Supply,
Grounding, and Decoupling Strategy section.
Digital Supply. There is an on-chip linear regulator providing the supply
voltage for the digital core. This pin is primarily provided for decoupling
purposes; however, the pin can also be overdriven, supplied by an
external 1.8 V supply if the user wants to use a more efficient supply to
minimize power dissipation. In this case, use the VREG_EN pin tied to
ground to disable the ADCVDD and DVDD regulators. See recommendations
for bypass capacitors in the Power Supply, Grounding, and Decoupling
Strategy section.
Analog Ground.
Digital Ground.
Enables or disables the internal voltage regulators used for ADCVDD and
DVDD. Tie this pin to AVDD to enable or tie this pin to ground to disable
the internal voltage regulators.
Analog Input, Left Arm (LA).
Analog Input, Left Leg (LL).
Analog Input, Right Arm (RA).
Analog Input, Chest Electrode 1 or Auxiliary Biopotential Input (V1).
Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2).
Rev. C | Page 16 of 85
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