EVM4717DBG View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'EVM4717DBG' PDF : 22 Pages View PDF
Edge4717D
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
VOS@IVMON
CM Linearity
Power Supply Sequencing
In order to avoid the possibility of latch-up, the following
power-up requirements must be satisified:
–3.5V
2 mV
CM Error = Slope
–2 mV
VCM@FORCE
9.5V
1. VEE ≤ GND ≤ VDD ≤ VCC at all times
2. VEE ≤ All inputs ≤ VCC
The following power supply sequencing can be used as a
guideline when operating the Edge4717D:
(Note: Slope may be negative)
Figure 2. Graphical Representation of
Common Mode Error
Transient Clamps
Power Up Sequence
1. VCC (substrate)
2. VEE/VDD
3. Digital Inputs
4. Analog Inputs
Power Down Sequence
1. Analog Inputs
2. Digital Inputs
3. VEE/VDD
4. VCC (substrate)
The Edge4717D has on-board transient clamps to limit
the voltage and current spikes that might result from either
changing the current range or changing the operating
mode.
Driven Guard Pin
The Edge4717D features a pin (per channel), GUARD,
which can be used to drive the guard traces of a FORCE/
SENSE pair. By surrounding FORCE and SENSE traces
with guard traces which connect to the GUARD pin, an
effective method to achieve minimal leakage can be
achieved.
2005 Semtech Corp. / Rev. 5, 10/14/05
10
www.semtech.com
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