FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
DSK CHG, Bit 7
The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the pin. The DSK
CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section
CR17 on page 109).
CONFIGURATION CONTROL REGISTER (CCR)
The Configuration Control Register (Bass Address + 7: Write-only) is write-only in all modes. Table 26 shows the
CCR in PC/AT mode and PS/2 mode. Table 27 shows the CCR in Model 30 mode.
PC/AT and PS/2 Interface Modes
RESET
CONDITION
Table 26 - CCR PC/AT and PS/2 Interface Modes
7
6
5
4
3
2
1
DRATE
SEL1
N/A N/A N/A N/A N/A N/A
1
0
DRATE
SEL0
0
Data Rate Select, Bits 0 - 1
These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values.
Reserved, Bits 2 - 7
Bits 2 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
Model 30 Interface Mode
Table 27 - CCR Model 30 Interface Mode
7
6
5
4
3
2
1
NOPREC
DRATE
SEL1
RESET
N/A N/A N/A N/A N/A
N/A
1
CONDITION
0
DRATE
SEL0
0
Data Rate Select, Bits 0 - 1
These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values.
No Precompensation, Bit 2
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30
register mode. Unaffected by software reset.
RESERVED, Bits 3 - 7
Bits 3 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
SMSC DS – FDC37N869
Page 31
Rev. 11/09/2000
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