FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
Table 30 - Status Register 2
BIT NO.
7
6
SYMBOL
CM
NAME
Control
Mark
5 DD
4 WC
3
2
1 BC
0 MD
Data Error
in Data
Field
Wrong
Cylinder
Bad
Cylinder
Missing
Data
Address
Mark
DESCRIPTION
Unused. This bit is always “0”.
Any one of the following:
1. Read Data command - the FDC encountered a deleted data
address mark.
2. Read Deleted Data command - the FDC encountered a data
address mark.
The FDC detected a CRC error in the data field.
The track address from the sector ID field is different from the track
address maintained inside the FDC.
Unused. This bit is always “0”.
Unused. This bit is always “0”.
The track address from the sector ID field is different from the track
address maintained inside the FDC and is equal to FF hex, which
indicates a bad track with a hard error according to the IBM soft-sectored
format.
The FDC cannot detect a data address mark or a deleted data address
mark.
Table 31 - Status Register 3
BIT NO.
7
6
SYMBOL
WP
NAME
Write
Protected
5
4 T0
3
2 HD
1,0 DS1,0
Track 0
Head
Address
Drive
Select
DESCRIPTION
Unused. This bit is always “0”.
Indicates the status of the WP pin. The Write Protected bit also depends
upon the state of the Force Write Protect bits in the Force FDD Status
Change configuration register (see section
CR17 on page 109).
Unused. This bit is always “1”.
Indicates the status of the TRK0 pin.
Unused. This bit is always “1”.
Indicates the status of the HDSEL pin.
Indicates the status of the DS1, DS0 pins.
Reset
There are three sources of system reset on the FDC: the RESET pin of the FDC37N869, a reset generated via a bit
in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All
resets take the FDC out of the power down state.
All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information,
and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
SMSC DS – FDC37N869
Page 33
Rev. 11/09/2000
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