FDC37N869 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

FDC37N869

5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications

SMSC -> Microchip 

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Reserved, Bits 4 - 5

Bits 4 to 5 are RESERVED. Reserved bits cannot be written and return 0 when read.

FIFOs Enabled, Bits 6 - 7

The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1.

FIFO

MODE

ONLY

BIT

3

0

0

INTERRUPT

IDENTIFICATION

REGISTER

BIT 2 BIT 1 BIT

0

00

1

11

0

0

10

0

1

10

0

0

01

0

0

00

0

Table 49 - Interrupt Control

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY

LEVEL

-

Highest

Second

Second

Third

Fourth

INTERRUPT

TYPE

None

Receiver

Line Status

Received

Data

Available

Character

Time-out

Indication

Transmitter

Holding

Register

Empty

MODEM

Status

INTERRUPT

SOURCE

None

Overrun Error,

Parity Error,

Framing Error

or Break

Interrupt

Receiver Data

Available

No Characters

Have Been

Removed

From or Input

to the RCVR

FIFO during

the last 4

Character

times and

there is at

least 1

character in it

during this

time

Transmitter

Holding

Register

Empty

Clear to Send

or Data Set

Ready or Ring

Indicator or

Data Carrier

Detect

INTERRUPT RESET

CONTROL

-

Reading the Line

Status Register

Read Receiver

Buffer or the FIFO

drops below the

trigger level.

Reading the

Receiver Buffer

Register

Reading the IIR

Register (if Source

of Interrupt) or

Writing the

Transmitter

Holding Register

Reading the

MODEM Status

Register

SMSC DS – FDC37N869

Page 61

Rev. 11/09/2000

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