REGISTER
ADDRESS*
ADDR = 1
DLAB = 1
REGISTER NAME
Divisor Latch (MS)
REGISTER
SYMBOL
DLM Bit 8
BIT 0
BIT 1
Bit 9
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Table 56 - Individual UART Channel Register Summary Continued
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4 Data Bit 5 Data Bit 6
Data Bit 7
Data Bit 2
Data Bit 3
Data Bit 4 Data Bit 5 Data Bit 6
Data Bit 7
Enable
Enable
0
0
0
0
Receiver Line MODEM
Status
Status
Interrupt
Interrupt
(ELSI)
(EMSI)
Interrupt ID Bit Interrupt ID Bit 0
(Note 5)
0
FIFOs
FIFOs
Enabled (Note Enabled
5)
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select (Note
6)
Reserved
Reserved RCVR Trigger RCVR
LSB
Trigger MSB
Number of
Stop Bits
(STB)
Parity Enable Even Parity
(PEN)
Select
(EPS)
Stick Parity Set Break
Divisor Latch
Access Bit
(DLAB)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity Error
(PE)
Framing Error
(FE)
Break
Interrupt (BI)
Transmitte
r Holding
Register
(THRE)
Transmitter
Empty (TEMT)
(Note 2)
Error in
RCVR FIFO
(Note 5)
Trailing Edge Delta Data Clear to
Data Set
Ring Indicator Carrier Detect Send (CTS) Ready
(TERI)
(DDCD)
(DSR)
Ring Indicator Data Carrier
(RI)
Detect (DCD)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Notes On Serial Port FIFO Mode Operation
GENERAL
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
SMSC DS – FDC37N869
Page 70
Rev. 11/09/2000