GL852G View Datasheet(PDF) - Genesys Logic
Part Name
Description
MFG CO.
'GL852G' PDF : 38 Pages View PDF
GL852G Datasheet
5.2 Configuration and I/O Settings
5.2.1 RESET Setting
GL852G’s power on reset can either be triggered by external reset or internal power good reset circuit. The
external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V
voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested
value refers to schematics) GL852G’s internal reset is designed to monitor silicon’s internal core power
(3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power
good voltage has been met, and the reset will be released after approximately 2.7 μS after power good.
GL852G’s reset circuit as depicted in the picture
PCB
VBUS
(External 5V)
R1
Silicon
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
R2
EXT
Global
Reset#
INT
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
Figure 5.3 - Power on Reset Diagram
To fully control the reset process of GL852G, we suggest the reset time applied in the external reset circuit
should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure.
Figure 5.4 - Power on Sequence of GL852G
©2012 Genesys Logic, Inc. - All rights reserved.
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