GS9035C View Datasheet(PDF) - Gennum -> Semtech
Part Name
Description
MFG CO.
'GS9035C' PDF : 14 Pages View PDF
DETAILED DESCRIPTION
The GS9035C receives either a single-ended or differential
PECL serial data stream at the DDI and DDI inputs. It locks
an internal clock to the incoming data and outputs the
differential PECL retimed data signal and recovered clock
on outputs SDO/SDO and SCO/SCO respectively. The
timing between the input, output, and clock signals is
shown below.
DDI
SDO
SCO
50%
Fig. 8 Input/Output Clock Signal Timing
The GS9035C reclocker contains four main functional
blocks: the Phase Locked Loop, Auto/Manual Data Rate
Select, Frequency Acquisition, and Logic Circuit.
1. PHASE LOCKED LOOP (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
2
DDI/DDI
PHASE
DETECTOR
INTERNAL
PLL CLOCK
DIVISION
CHARGE
PUMP
VCO
LF+ LFS LF-
RLF CLF1
CLF2
LOOP
FILTER
RVCO
Fig. 9 Simplified Diagram of the PLL
1.1 VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 143 and 360Mb/s and has a pull range of
-13 +25% about the center frequency depending on the
signal data rate. A single low impedance external resistor,
RVCO, sets the VCO center frequency (see Figure 9). The
low impedance RVCO minimizes thermal noise and reduces
the PLL's sensitivity to PCB noise.
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the ƒL curve. For all other
SMPTE/SS0 combinations, the VCO center frequency
corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL).
800
700
600
500
400
ƒH
300
200
100
0
0
ƒL
SMPTE=1
SSO=1
200 400 600
800 1000 1200 1400 1600 1800
RVCO (Ω)
Fig. 10 VCO Frequency vs. RVCO
The recommended RVCO value for auto rate SMPTE 259M
applications is 365Ω.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 360Mb/s. The divider modulus is set
by the AUTO/MAN, SMPTE, and SS[1:0] pin
(see Auto/Manual Data Rate Select section for further
details).
When the input data stream is removed for an excessive
period of time (see AC electrical characteristics table), the
VCO frequency can drift from the previously locked
frequency up to the maximum shown in Table 1.
TABLE 1: Frequency Drift Range (when PLL loses lock)
LOSES LOCK FROM
MIN (%)
MAX(%)
143Mb/s lock
-21
21
177Mb/s lock
-12
26
270Mb/s lock
-13
28
360 Mb/s lock
-13
24
GENNUM CORPORATION
6 of 14
20582 - 3
Share Link: 
