HC4P5524-5 View Datasheet(PDF) - Harris Semiconductor
Part Name
Description
MFG CO.
'HC4P5524-5' PDF : 12 Pages View PDF
HC-5524
Electrical Specifications
Typical Parameters are at TA = 25oC, VB+ = 5V, VB- = -24V, AG = DG = BG = 0V. Min-Max Parameters are Over
Operating Positive and Negative Battery Voltages and Over the Operating Temperature Range. All Parameters are
Specified at 600Ω 2-Wire Terminating Impedance, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
TTL/CMOS Logic Inputs (F0, F1, RS, TST, PRI)
Logic ‘0’ VIL
-
-
0.8
V
Logic ‘1’ VIH
Input Current (F0, F1, RS, TST, PRI)
Logic Outputs
Logic ‘0’ VOL
Logic ‘1’ VOH
Power Dissipation On Hook
IB+
IB-
IB+
IB-
UNCOMMITED OP AMP PARAMETERS
0V ≤ VIN ≤ 5V
ILOAD = 800µA
ILOAD = 40µA
Relay Drivers Off
∞ VB+ = 5.25V, VB- = -28V, RLOOP =
∞ VB+ = 5.25V, VB- = -28V, RLOOP =
VB+ = 5V, VB- = -24V, RLOOP = 600Ω
VB+ = 5V, VB- = -24V, RLOOP = 600Ω
2.0
-
5.5
V
-
-
±100
µA
-
0.1
0.5
V
2.7
-
-
V
-
60
-
mW
-
-
4
mA
-4
-
-
mA
-
3
6
mA
-28
-24
-
mA
Input Offset Voltage
-
±5
-
mV
Input Offset Current
-
±10
-
nA
Differential Input Resistance
(Note 3)
-
1
-
MΩ
Output Voltage Swing
Small Signal GBW
RL = 10kΩ
(Note 3)
-
±3
-
VP-P
-
1
-
MHz
NOTES:
2. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily implied.
3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon
initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and spec-
ification compliance.
Pin Descriptions
DIP/SO
IC
PLCC
1
2
2
3
3
4
4
8
5
9
6
10
SYMBOL
DESCRIPTION
AG
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and
(Note 4) receive input terminals.
VB+
Positive Voltage Source - Most Positive Supply.
C1
Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground. Re-
quired for proper operation of the loop current limiting function.
F1
Function Address #1 - A TTL and CMOS compatible input used with F0 function address line to externally
select logic functions. The three selectable functions are mutually exclusive. See Truth Table on front
page. F1 should be toggled high after power is applied.
F0
Function Address #0 - A TTL and CMOS compatible input used with F1 function address line to externally
select logic functions. The three selectable functions are mutually exclusive. See Truth Table on front
page.
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock is arranged such that a positive
pulse (50µs - 500µs) occurs on the zero crossing of the ring voltage source, as it appears at the RFS
terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing
and for Ring injected systems, on the positive going zero crossing. This ensures that the ring delay acti-
vates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not re-
quired, the pin should be tied to +5V.
4
Share Link: 
