HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
· ADRH, ADRL Register
ADRH
ADRL
Bit 7 6 5 4 3 2 1 0 7 6 5 4 3
Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ¾
R/W R R R R R R R R R R R R ¾
POR x x x x x x x x x x x x ¾
unimplemented, read as ²0²
D11~D0: ADC conversion data
· ADCR Register
210
¾¾¾
¾¾¾
¾¾¾
²x² unknown
Bit
Name
R/W
POR
7
START
R/W
0
6
EOCB
R
1
5
PCR3
R/W
0
4
PCR2
R/W
0
3
PCR1
R/W
0
2
PCR0
R/W
0
1
ACS1
R/W
0
0
ACS0
R/W
0
Bit 7
Bit 6
Bit 5~2
Bit 1~0
START: Start the A/D conversion
0®1®0 : start
0®1 : reset the A/D converter and set EOCB to ²1²
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
PCR3, PCR2, PCR1, PCR0: A/D channel configuration
0: I/O
1: analog input n (n=0~3)
If PCR0~PCR3 are all zero, the ADC circuit is power off to reduce power consumption
ACS1 ~ ACS0: Select A/D channel
00: AN0
01: AN1
10: AN2
11: AN3
· ACSR Register
Bit
7
6
5
4
3
2
1
0
Name
TEST ADONB
¾
¾
¾
ADCS2 ADCS1 ADCS0
R/W
R/W
R/W
¾
¾
¾
R/W
R/W
R/W
POR
1
0
¾
¾
¾
0
0
0
Bit 7
Bit 6
Bit 5~3
Bit 2~0
TEST: for test mode use only
ADONB: ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
Note: 1. it is recommended to set ADONB=1 before entering sleep for saving power.
2. ADONB=1 will power down the ADC module.
unimplemented, read as ²0²
ADCS2~ADCS0 : Select A/D converter clock source
000: system clock/2
001: system clock/8
010: system clock/32
011: undefined, can¢t be used.
100: system clock
101: system clock/4
110: system clock/16
111: undefined, can¢t be used.
Rev.1.00
44
June 9, 2011