HT48R01B-1 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R01B-1' PDF : 71 Pages View PDF
HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
The ADCR control register also contains the
PCR3~PCR0 bits which determine which pins on
PA0~PA3 are used as analog inputs for the A/D converter
and which pins are to be used as normal I/O pins. Note
that if the PCR3~PCR0 bits are all set to zero, then all the
PA0~PA3 pins will be setup as normal I/Os.
A/D Operation
The START bit in the register is used to start and reset
the A/D converter. When themicrocontroller sets this bit
from low to high and then low again, an analog to digital
conversion cycle will be initiated. When the START bit is
brought from low to high but not low again, the EOCB bit
in the ADCR register will be set to a ²1² and the analog
to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal
analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to ²0² by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the ADCS2,
ADCS1 and ADCS0 bits in the ACSR register.
The A/D converter overall on/off control is a function of
both the ADONB bit in the ACSR register and the PCRn
bits in the ADCR register as shown in the table. Either
the ADONB bit cleared to zero or the PCRn bits set to a
zero value will switch off the A/D converter. These are
important consideration in power sensitive applications
and must be taken into account if power consumption is
to be minimised. As the table illustrates, execution of the
HALT instruction has no effect on the A/D converter
on/off control and subsequently its power consumption.
PCRn
Bits
=0
>0
>0
HALT
Instruction
X
X
X
ADONB
Bit
X
0
1
ADC
On/Off
Off
On
Off
Note: X: Don¢t care
A/D Converter On/Off Control
Although the A/D clock source is determined by the sys-
tem clock fSYS, and by bits ADCS2, ADCS1 and ADCS0,
there are some limitations on the A/D clock source
speed range that can be selected. As the recommended
range of permissible A/D clock period, tAD, is from 0.5ms
to 10ms, care must be taken for the selected system
clock speeds. For example, if the system clock operates
at a frequency of 2MHz or 4MHz, the ADCS2, ADCS1
and ADCS0 bits should not be set to ²010² or ²100² re-
spectively. Doing so will give A/D clock periods that are
greater than the maximum A/D clock period or less than
the minimum A/D clock period which may result in inac-
curate A/D conversion values. Refer to the following ta-
ble for examples, where values marked with an asterisk
* show where, depending upon the system clock speed,
special care must be taken, as the values may be out of
the specified A/D Clock Period range.
fSYS
1MHz
2MHz
4MHz
8MHz
12MHz
ADCS2,
ADCS1,
ADCS0=000
(fSYS/2)
2ms
1ms
500ns
250ns*
167ns*
ADCS2,
ADCS1,
ADCS0=001
(fSYS/8)
8ms
4ms
2ms
1ms
667ns
A/D Clock Period (tAD)
ADCS2,
ADCS1,
ADCS0=010
(fSYS/32)
ADCS2,
ADCS1,
ADCS0=100
(fSYS)
ADCS2,
ADCS1,
ADCS0=101
(fSYS/4)
32ms*
1ms
4ms
16ms
500ns
2ms
8ms*
250ns*
1ms
4ms
125ns*
500ns
2.67ms
83ns*
333ns*
ADCS2,
ADCS1,
ADCS0=110
(fSYS/16)
ADCS2,
ADCS1,
ADCS0=011,
111
16ms*
Undefined
8ms
Undefined
4ms
Undefined
2ms
Undefined
1ms
Undefined
A/D Clock Period Examples
Rev.1.00
45
June 9, 2011
Share Link: 
