HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
SPI Interface
The devices contain an independent SPI function. It is
important not to confuse this independent SPI function
with the additional one contained within the combined
SIM function, which is described in another section of
this datasheet.
The SPI interface is a full duplex serial data link, origi-
nally designed by Motorola, which allows multiple de-
vices connected to the same SPI bus to communicate
with each other. The devices communicate using a mas-
ter/slave technique where only the single master device
can initiate a data transfer. A simple four line signal bus
is used for all communication.
SPI Interface Communication
Four lines are used for each function. These are, SDI1
Serial Data Input, SDO1 Serial Data Output, SCK1 Se-
rial Clock and SCS1 Slave Select. Note that the condi-
tion of the Slave Select line is conditioned by the CSEN1
bit in the SPICTL1 control register. If the CSEN1 bit is
high then the SCS1 line is active while if the bit is low
then the SCS line will be in a floating condition. The ac-
companying timing diagram depicts the basic timing
protocol of the SPI bus.
SPI Registers
There are three registers for control of the SPI Interface.
These are the two control registers SPICTL0 and
SPICTL1 and the SBDR data register. The SPICTL0
register is used for the overall SPI enable/disable, mas-
ter/slave selection and clock selection. The SPICTL1
register is used for SPI setup including, clock polarity,
edge selection as well as certain status flags. The
SBDR register is used for data storage. After Power on,
the contents of the SBDR register will be in an unknown
condition. Note that data written to the SBDR register
will only be written to the TXRX buffer, whereas data
read from the SBDR register will actual be read from the
register.
· SPIDR Register
Bit
Name
R/W
POR
7
SPD7
R/W
x
6
SPD6
R/W
x
5
SPD5
R/W
x
4
SPD4
R/W
x
Bit 7
SPD7~SPD0: SPI data
· SPICTL0 Register
Bit
7
6
5
4
Name
SP12
SP11
SP10
¾
R/W
R/W
R/W
R/W
¾
POR
1
1
1
0
Bit 7~5
Bit 4~2
Bit 1
Bit 0
SPI2~SPI0: Master/Slave Clock Select
000: SPI master, fSYS/4
001: SPI master, fSYS/16
010: SPI master, fSYS/64
011: SPI master, fSUB
100: SPI master, timer 0 output/2 (PFD0)
101: SPI slave
unimplemented, read as ²0²
SPIEN: SPI Enable/Disable
0: disable
1: enable
unimplemented, read as ²0²
3
SPD3
R/W
x
3
¾
¾
0
2
SPD2
R/W
x
1
SPD1
R/W
x
0
SPD0
R/W
x
²x² unknown
2
1
0
¾
SPIEN
¾
¾
¾
¾
0
0
0
Rev. 1.30
77
December 26, 2014