HT56R26 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R26' PDF : 134 Pages View PDF
HT56R22/HT56R23/HT56R24/HT56R25/HT56R26
SPI Bus Enable/Disable
To enable the SPI bus, the SBEN bit should be set high,
then wait for data to be written to the SBDR (TXRX
buffer) register. For the Master Mode, after data has
been written to the SBDR (TXRX buffer) register then
transmission or reception will start automatically. When
all the data has been transferred, the TRF1 bit should be
set. For the Slave Mode, when clock pulses are re-
ceived on SCK1, data in the TXRX buffer will be shifted
out or data on SDI1 will be shifted in. When the SPI bus
is disabled, SCK1, SDI1, SDO1 and SCS1 will be setup
as I/O pins.
SPI Operation
The SPI is selected using the application program. All
communication is carried out using the 4-line interface
for both Master or Slave Mode. The CSEN1 bit in the
SPICTL1 register controls the SCSB line of the SPI in-
terface. Setting this bit high, will enable the SPI interface
by allowing the SCS1 line to be active, which can then
be used to control the SPI interface. If the CSEN1 bit is
low, the SCS1 line will be in a floating condition and can
therefore not be used for control of the SPI interface.
When the CSEN1 bit is set high then SDI1 line will be
placed in a floating condition and the SDO1 line will be
high. If in the Master Mode, the SCK1 line will be either
high or low depending upon the clock polarity configura-
tion option. If in the Slave Mode the SCK1 line will be in a
floating condition. If CSEN1 is low then the bus will be
disabled and SCS1, SDI1, SDO1 and SCK1 will all be in
a floating condition. The SPI function keeps running in
the IDLE mode - the SPI module can still operate after a
HALT instruction is executed. The CKEG1 and CKPOL1
bits must be setup before the SPI is enabled; otherwise
undesired clock edge may be generated.
In the Master Mode, the Master will always generate the
clock signal. The clock and data transmission will be ini-
tiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Modes:
· Master Mode
¨ Step 1
Setup the SPI2~SPI0 bits in the SPICTL0 control
register to select the Master Mode and the required
clock speed. Values of 000~101 can be selected.
¨ Step 2
Setup the SPIEN bit and setup the MLS1 bit to
choose if the data is MSB or LSB first, this must be
same as the Slave device.
¨ Step 3
Setup the CSEN1 bit in the SPICTL1 control regis-
ter to enable the SPI interface.
¨ Step 4
For write operations: write the data to the SBDR
register, which will actually place the data into the
TXRX buffer. Then use the SCK1 and SCS1 lines to
output the data. Then goto to step 5. For read oper-
ations: the data transferred in on the SDI1 line will
be stored in the TXRX buffer until all the data has
been received at which point it will be latched into
the SBDR register.
¨ Step 5
Check the WCOL1 bit, if set high then a collision er-
ror has occurred so return to Step 4. If zero then go
to the following step.
¨ Step 6
Check the TRF1 bit or wait for an SPI serial bus in-
terrupt.
¨ Step 7
Read data from the SBDR register.
¨ Step 8
Clear flag TRF1.
¨ Step 9
Goto step 4.
· Slave Mode
¨ Step 1
Setup the SPI2~SPI0 bits to 101 to select the Slave
Mode.
¨ Step 2
Setup the SPIEN bit and setup the MLS1 bit to
choose if the data is MSB or LSB first, this must be
same as the Master device.
¨ Step 3
Setup the CSEN1 bit in the SPICTL1 control regis-
ter to enable the SPI interface.
¨ Step 4
For write operations: write data to the SBDR regis-
ter, which will actually place the data into the TXRX
register, then wait for the master clock and SCS1
signal. After this goto Step 5. For read operations:
the data transferred in on the SDI1 line will be
stored in the TXRX buffer until all the data has been
received at which point it will be latched into the
SBDR register.
¨ Step 5
Check the WCOL1 bit, if set high then a collision er-
ror has occurred so return to step 4. If equal to zero
then goto the following step.
¨ Step 6
Check the TRF1 bit or wait for an SPI interrupt.
¨ Step 7
Read data from the SBDR register.
¨ Step 8
Clear TRF1
¨ Step 9
Goto step 4
Rev. 1.30
79
December 26, 2014
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