HT56R666 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R666' PDF : 104 Pages View PDF
HT56R66/HT56R666
fSYS
1MHz
2MHz
4MHz
8MHz
12MHz
ADCS2, ADCS1,
ADCS0=000
(fSYS/2)
2ms
1ms
500ns
250ns*
167ns*
A/D Clock Period (tAD)
ADCS2, ADCS1,
ADCS0=001
(fSYS/8)
ADCS2, ADCS1,
ADCS0=010
(fSYS/32)
8ms
32ms
4ms
16ms
2ms
8ms
1ms
4ms
667ns
2.67ms
ADCS2, ADCS1,
ADCS0=011
Undefined
Undefined
Undefined
Undefined
Undefined
A/D Clock Period Examples
b7
TEST ADO NB
b0
A D C S 2 A D C S 1 A D C S 0 A C S R R e g is te r
S e le c t A /D c o n v e r te r c lo c k s o u r c e
ADCS2
0
0
0
0
ADCS1
0
0
1
1
ADCS0
0
1
0
1
: s y s te m c lo c k /2
: s y s te m c lo c k /8
: s y s te m c lo c k /3 2
: u n d e fin e d
1
0
1
0
1
1
1
1
0
: s y s te m c lo c k
1
: s y s te m c lo c k /4
0
: s y s te m c lo c k /1 6
1
: u n d e fin e d
N o t im p le m e n te d , r e a d a s " 0 "
A /D O n /O ff c o n tr o l b it
1 : d is a b le
0 : e n a b le
F o r te s t m o d e u s e o n ly
A/D Converter Control Register - ACSR
A/D Input Pins
All of the A/D analog input pins are pin-shared with the
I/O pins on Port B. Bits PCR2~PCR0 in the ADCR regis-
ter, determine whether the input pins are setup as nor-
mal Port B input/output pins or whether they are setup
as analog inputs. In this way, pins can be changed under
program control to change their function from normal I/O
operation to analog inputs and vice versa. Pull-high re-
sistors, which are setup through register programming,
apply to the input pins only when they are used as nor-
mal I/O pins, if setup as A/D inputs the pull-high resistors
will be automatically disconnected. Note that it is not
necessary to first setup the A/D pin as an input in the
PBC port control register to enable the A/D input as
when the PCR2~PCR0 bits enable an A/D input, the sta-
tus of the port control register will be overridden. The
A/D converter has its own power supply pins AVDD and
AVSS and a VREF reference pin. The analog input val-
ues must not be allowed to exceed the value of VREF.
Initialising the A/D Converter
The internal A/D converter must be initialised in a special
way. Each time the Port B A/D channel selection bits are
modified by the program, the A/D converter must be
re-initialised. If the A/D converter is not initialised after the
channel selection bits are changed, the EOCB flag may
have an undefined value, which may produce a false end
of conversion signal. To initialise the A/D converter after
the channel selection bits have changed, then, within a
time frame of one to ten instruction cycles, the START bit
in the ADCR register must first be set high and then im-
mediately cleared to zero. This will ensure that the EOCB
flag is correctly set to a high condition.
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D con-
version process.
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCS2, ADCS1 and ADCS0 in the
register.
· Step 2
Enable the A/D by clearing the in the ACSR register to
zero.
· Step 3
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS2~ACS0 bits which are also contained in the reg-
ister.
· Step 4
Select which pins on Port B are to be used as A/D in-
puts and configure them as A/D input pins by correctly
programming the PCR2~PCR0 bits in the ADCR reg-
ister. Note that this step can be combined with Step 2
into a single ADCR register programming operation.
Rev. 1.40
51
May 11, 2012
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