HT56R66/HT56R666
¨ Rising or falling active clock edge
¨ WCOL and CSEN bit enabled or disable select
The status of the SPI interface pins is determined by a
number of factors such as whether the device is in the
master or slave mode and upon the condition of cer-
tain control bits such as CSEN, SIMEN and SCS. In
the table I, Z represents an input floating condition.
There are several configuration options associated
with the SPI interface. One of these is to enable the
SIM function which selects the SIM pins rather than
normal I/O pins. Note that if the configuration option
does not select the SIM function then the SIMEN bit in
the SIMCTL0 register will have no effect. Another two
SIM configuration options determine if the CSEN and
WCOL bits are to be used.
Configuration Option
Function
SIM Function
SIM interface or I/O pins
SPI CSEN bit
Enable/Disable
SPI WCOL bit
Enable/Disable
SPI Interface Configuration Options
SPI Registers
There are three internal registers which control the over-
all operation of the SPI interface. These are the SIMDR
data register and two control registers SIMCTL0 and
SIMCTL2. Note that the SIMCTL1 register is only used
by the I2C interface.
Pin
Master/Salve
SIMEN=0
Master - SIMEN=1
CSEN=0
CSEN=1
CSEN=0
Slave - SIMEN=1
CSEN=1
SCS=0
CSEN=1
SCS=1
SCS
Z
Z
L
Z
I, Z
I, Z
SDO
Z
O
O
O
O
Z
SDI
Z
I, Z
I, Z
I, Z
I, Z
Z
SCK
Z
H: CKPOL=0
L: CKPOL=1
H: CKPOL=0
L: CKPOL=1
I, Z
I, Z
Z
Note: ²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)
SPI Interface Pin Status
C K E G b it
C K P O L b it
S C K P in
fS Y S
fS U B
T im e r /E v e n t C o u n te r
S C S P in
C S E N b it
D a ta B u s
S IM D R
T x /R x S h ift R e g is te r
C lo c k
E d g e /P o la r ity
C o n tro l
C lo c k
S o u r c e S e le c t
B usy
S ta tu s
S D I P in
S D O P in
E n a b le /D is a b le
C o n fig u r a tio n
O p tio n
W C O L F la g
T R F F la g
C o n fig u r a tio n
O p tio n
E n a b le /D is a b le
SPI Block Diagram
Rev. 1.40
55
May 11, 2012