HT56R666 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R666' PDF : 104 Pages View PDF
HT56R66/HT56R666
· SRW Bit
The SRW bit in the SIMCTL1 register defines whether
the microcontroller slave device wishes to read data
from the I2C bus or write data to the I2C bus. The
microcontroller should examine this bit to determine if
it is to be a transmitter or a receiver. If the SRW bit is
set to ²1² then this indicates that the master wishes to
read data from the I2C bus, therefore the
microcontroller slave device must be setup to send
data to the I2C bus as a transmitter. If the SRW bit is
²0² then this indicates that the master wishes to send
data to the I2C bus, therefore the microcontroller slave
device must be setup to read data from the I2C bus as
a receiver.
· Acknowledge Bit
After the master has transmitted a calling address,
any slave device on the I2C bus, whose own internal
address matches the calling address, must generate
an acknowledge signal. This acknowledge signal will
inform the master that a slave device has accepted its
calling address. If no acknowledge signal is received
by the master then a STOP signal must be transmitted
by the master to end the communication. When the
HAAS bit is high, the addresses have matched and
the microcontroller slave device must check the SRW
bit to determine if it is to be a transmitter or a receiver.
If the SRW bit is high, the microcontroller slave device
should be setup to be a transmitter so the HTX bit in
the SIMCTL1 register should be set to ²1² if the SRW
bit is low then the microcontroller slave device should
be setup as a receiver and the HTX bit in the SIMCTL1
register should be set to ²0².
· Data Byte
The transmitted data is 8-bits wide and is transmitted
after the slave device has acknowledged receipt of its
slave address. The order of serial bit transmission is
the MSB first and the LSB last. After receipt of 8-bits of
data, the receiver must transmit an acknowledge sig-
nal, level ²0², before it can receive the next data byte.
If the transmitter does not receive an acknowledge bit
signal from the receiver, then it will release the SDA
line and the master will send out a STOP signal to re-
lease control of the I2C bus. The corresponding data
will be stored in the SIMDR register. If setup as a
transmitter, the microcontroller slave device must first
write the data to be transmitted into the SIMDR regis-
ter. If setup as a receiver, the microcontroller slave de-
vice must read the transmitted data from the SIMDR
register.
SCL
SDA
· Receive Acknowledge Bit
When the receiver wishes to continue to receive the
next data byte, it must generate an acknowledge bit,
known as TXAK, on the 9th clock. The microcontroller
slave device, which is setup as a transmitter will check
the RXAK bit in the SIMCTL1 register to determine if it
is to send another data byte, if not then it will release
the SDA line and await the receipt of a STOP signal
from the master.
Peripheral Clock Output
The Peripheral Clock Output allows the device to supply
external hardware with a clock signal synchronised to
the microcontroller clock.
Peripheral Clock Operation
As the peripheral clock output pin, PCLK, is shared with
one of the LCD segment lines, the required pin function
is chosen via PCKEN in SIMCTL0 register. The Periph-
eral Clock function is controlled using the SIMCTL0 reg-
ister. The clock source for the Peripheral Clock Output
can originate from either the Timer/Event Counter 0 di-
vided by two or a divided ratio of the internal fSYS clock.
The PCKEN bit in the SIMCTL0 register is the overall
on/off control, setting the bit high enables the Peripheral
Clock, clearing it disables it. The required division ratio
of the system clock is selected using the PCKPSC0 and
PCKPSC1 bits in the same register. If the system enters
the Sleep Mode this will disable the Peripheral Clock
output.
PCKPSC0 PCKPSC1 PCKEN
fS Y S
T im e r /E v e n t
C o u n te r 0 ¸ 2
¸ 1,4,8
P C LK
orS E G P C LK
S e le c t o r
SEG
S le e p M o d e
Peripheral Clock Block Diagram
S ta r t b it
D a ta D a ta
s ta b le a llo w
change
Data Timing Diagram
S to p b it
Rev. 1.40
64
May 11, 2012
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