HT56R666 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT56R666' PDF : 104 Pages View PDF
HT56R66/HT56R666
b7
b0
S IM 2 S IM 1 S IM 0 P C K E N P C K P S C 1 P C K P S C 0 S IM E N
S IM C T L 0 R e g is te r
N o t im p le m e n te d , r e a d a s '0 "
S P I/I2C O n /O f c o n tro l
1 : e n a b le
0 : d is a b le
P C K c lo c k s e le c t
PCKPSC1 PCKPSC0
0
0
0
1
1
0
1
1
C lo c k S o u r c e
fS Y S
fS Y S /4
fS Y S /8
T im e r /E v n e t C o u n te r 0 ¸ 2
P e r ip h e r a l c lo c k e n a b le
1 : c lo c k a n d o u tp u t e n a b le
0 : c lo c k a n d o u tp u t d is a b le
S P I M a s te r /S la v e a n d c lo c k c o n tr o l
- d e s c r ib e d e ls e w h o s e
Peripheral Clock Output Control - SIMCTL0
Buzzer
Operating in a similar way to the Programmable Fre-
quency Divider, the Buzzer function provides a means of
producing a variable frequency output, suitable for ap-
plications such as Piezo-buzzer driving or other external
circuits that require a precise frequency generator. The
BZ and BZ pins form a complementary pair, and are
pin-shared with I/O pins, PA0 and PA1. A configuration
option is used to select from one of three buzzer options.
The first option is for both pins PA0 and PA1 to be used
as normal I/Os, the second option is for both pins to be
configured as BZ and BZ buzzer pins, the third option
selects only the PA0 pin to be used as a BZ buzzer pin
with the PA1 pin retaining its normal I/O pin function.
Note that the BZ pin is the inverse of the BZ pin which to-
gether generate a differential output which can supply
more power to connected interfaces such as buzzers.
The buzzer is driven by the internal clock source, , which
then passes through a divider, the division ratio of which
is selected by configuration options to provide a range of
buzzer frequencies from fS/22 to fS/29. The clock source
that generates fS, which in turn controls the buzzer fre-
quency, can originate from three different sources, the
32768Hz oscillator, the 32K_INT oscillator or the Sys-
tem oscillator/4, the choice of which is determined by
the fS clock source configuration option. Note that the
buzzer frequency is controlled by configuration options,
which select both the source clock for the internal clock
fS and the internal division ratio. There are no internal
registers associated with the buzzer frequency.
If the configuration options have selected both pins PA0
and PA1 to function as a BZ and BZ complementary pair
of buzzer outputs, then for correct buzzer operation it is
essential that both pins must be setup as outputs by set-
ting bits PAC0 and PAC1 of the PAC port control register
to zero. The PA0 data bit in the PA data register must
also be set high to enable the buzzer outputs, if set low,
both pins PA0 and PA1 will remain low. In this way the
single bit PA0 of the PA register can be used as an on/off
control for both the BZ and BZ buzzer pin outputs. Note
that the PA1 data bit in the PA register has no control
over the BZ buzzer pin PA1.
fS Y S /4
32768H z
3 2 K _ IN T
fS S o u rc e
C o n fig u r a tio n
O p tio n
fS
C o n fig u r a tio n O p tio n
D iv id e b y 2 2 ~ 2 9
BZ
BZ
Buzzer Function
Rev. 1.40
65
May 11, 2012
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