HT66F016 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F016' PDF : 116 Pages View PDF
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016R/HT66F017R/HT68F016R/HT68F017R
· 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
0
Period
Duty
CCRP ´ 256
65536
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128
The CTM PWM output frequency = (fSYS/4) / (2´256) = fSYS/2048 = 7.8125 kHz, duty = 128 / (2´256) = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
· 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
Period
1~255
0
CCRA
Duty
CCRP ´ 256
65536
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-
cle is defined by the (CCRP´256) except when the CCRP value is equal to 0.
Counter Value
CCRA
CCRP
Counter cleared
by CCRA
TnDPX = 1; TnM [1:0] = 10
Counter Reset when
TnON returns high
Pause Resume
Counter Stop if
TnON bit low
TnON
Time
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM Mode -- TnDPX = 1
PWM resumes
operation
Output controlled by
other pin-shared function
Output Inverts
when TnPOL = 1
Note:
1. Here TnDPX = 1 -- Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.40
61
November 22, 2016
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