ICS1523MLF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1523MLF' PDF : 21 Pages View PDF
ICS1523
Video Clock Synthesizer with I2C Programmable Delay
11.2 Programming Flow for Modifying PLL and DPA Settings
BEGIN
Determine Horizontal Total
HTOTAL
Program Input Control Register Reg0x0
Typically = 41h
(Coast disabled, Positive edge of HSYNC, Internal Feedback,
FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin
Program Loop Control Register Reg0x1
VCO Divider 0x1:5~4 = (Maximum value where
Required Output Frequency * VCOD < 500 MHz)
Typical Charge Pump Current 0x1:2~0= 011b
Program Feedback Divider Reg0x2, Reg0x3
Internal Feedback Divider (0x3 & 0x2) = HTOTAL - 8
Program Internal Filter Reg0x4
Select Internal Filter 0x4:7 = 1
Program DPA Reg0x5
DPA Resolution 0x5 = (Value From Note 8 Table)
DPA Offset, 0x4:5~0 = 0
Program Output Control Reg0x6
Enable the desired outputs
Program OSC Divider Reg0x7
Select Desired Input Reg0x7:7
Select OSC divider value (if needed)
Decrement Charge
Pump Current
Reg0x1:2~0
Full S/W Reset
Reg0xA = 5Ah
PLL LOCKED?
No
LOCK Pin or
Read 0x12:1
Yes
Correct Phase
Relationship?
Yes
END
Increment DPA
No
Offset
Reg0x4
MDS 1523 Y
13
Revision 110905
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
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