ICS1523MLF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1523MLF' PDF : 21 Pages View PDF
ICS1523
Video Clock Synthesizer with I2C Programmable Delay
12.2 Timing for 0x0:2=1
Figure 12-3 0x0:2=1 Timing Diagram
Table 12-3 0x0:2=1 Timing Values
Symbol Parameter
T2 HSYNC Low to FUNC High Delay
T3 HSYNC Low to PECL CLK+ High Delay
(DPA Offset = 0)
T4 PECL Clock to SSTL_3 Clock Delay
T5 PECL Clock to FUNC Delay
T6 PECL Clock to PECL/2 Clock
T7 PECL Clock to SSTL_3 CLK/2 Delay
T8 PECL Clock High Time
Minimum
-
0
0.6
0.6
0.4
-
Typical
T8 + T3
10
0.2
1.0
1.0
0.9
0.5
Maximum
-
0.6
1.6
1.6
1.2
-
Units
ns
ns
ns
ns
ns
ns
UI
MDS 1523 Y
16
Revision 110905
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
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