ICS1523MLF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1523MLF' PDF : 21 Pages View PDF
ICS1523
Video Clock Synthesizer with I2C Programmable Delay
Parameter
Symbol
Min.
Max.
Analog Input (HSYNC)
Input High Voltage
VIH
1.7
5.5
Input Low Voltage
VIL
VSS - 0.3
1.1
Digital Inputs (SDA, SCL, EXTFB, OSC, I2CADDR)
Input High Voltage
Input Low Voltage
Input Hysteresis
POR Threshold
VIH
2
5.5
VIL
VSS - 0.3
0.8
-
0.2
0.6
-
VSS
1.8
SDA Digital Output
SDA Output Low Voltage
VOL
0.4
SDA Output High Voltage
VOH
6.0
PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)
Output High Voltage
VOH
-
Maximum Output Frequency
FP MAX
-
Output Low Voltage *
VOL
1.0
VDD
250
-
Duty Cycle
PDC
45
55
Transition Time - Rise
TPR
-
1.0
Transition Time - Fall
TPF
-
1.2
SSTL_3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
Output Resistance
RO
-
80
Maximum Output Frequency
Fs MAX
-
150
Duty Cycle
SDC
45
55
Clock and FUNC
Transition Time - Rise
TCR
-
1.6
Clock and FUNC
Transition Time - Fall
TCF
-
1.0
LOCK/REF Transition Time -
TLR
Rise
-
3.0
LOCK/REF Transition Time - Fall
TLF
-
2.0
Units
V
V
Notes
V
V
V
V
Voltage that resets
register values
V
IOUT = 3ma
V
Determined by
external Rset
resistor
V
MHz
V
%
ns
ns
IOUT=0
VDDD = 3.3 V
IOUT =
Programmed Value
1
2
2
2
Ω
MHz
%
ns
ns
ns
ns
1 V < VO < 2 V
VDDD = 3.3 V
3
3
3
3
3
Note 1- VOL must not fall below the level given so that the correct value for IOUT can be maintained.
Note 2- Measured at 135MHz, 3.6 VDC, 0oC, 20 pF, with 75 Ω Termination
Note 3- Measured at 135MHz, 3.6 VDC, 0oC, 20 pF, Unterminated
MDS 1523 Y
19
Revision 110905
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
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