ICS1893AGILF View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS1893AGILF' PDF : 135 Pages View PDF
ICS1893AG Data Sheet - Preliminary
Chapter 6 Interface Overviews
6.1 MII Data Interface
The ICS1893AG’s MAC Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or
100 Mbps. The ICS1893AG MAC/Repeater Interface is configured for the MII Data Interface mode, data is
transferred between the PHY and the MAC as framed, 4-bit parallel nibbles. In addition, the interface also
provides status and control signals to synchronize the transfers.
The ICS1893AG provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a
transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles).
• The ICS1893AG’s MII transmit data path includes the following:
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
• The ICS1893AG’s MII receive data path includes the following:
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by
the ICS1893AG (that is, the ICS1893AG sources the TXCLK and RXCLK signals to the MAC/repeater).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICS1893AG is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
• Half-duplex mode, the ICS1893AG asserts the Carrier Sense signal when data is being either
transmitted or received. While operating in half-duplex mode, the ICS1893AG also asserts its Collision
Detect signal to indicate that data is being received while a transmission is in progress.
• Full-duplex mode, the ICS1893AG asserts the Carrier Sense signal only when receiving data and forces
the Collision Detect signal to remain inactive.
As mentioned in Section 5.1.1.3, “Hot Insertion”, the ICS1893AG design allows hot insertion of its MII. That
is, it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1893AG isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit
pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the
ICS1893AG enables its MII and enables its Twisted-Pair Transmit signals.
ICS1893AG, Rev A 04/14/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
24
April, 2005
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