ICS1893BYI-10LF View Datasheet(PDF) - Integrated Circuit Systems
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MFG CO.
'ICS1893BYI-10LF' PDF : 143 Pages View PDF
ICS1893BY-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.9 10M Media Independent Interface: Receive Latency
Table 9-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of
signals on the following pins:
• TP_RX (that is, the MII TP_RXP and TP_RXN pins)
• RXCLK
• RXD
Figure 9-10 shows the timing diagram for the time periods.
Table 9-16. 10M MII Receive Latency
Time
Period
Parameter
t1 First Bit of /5/ on TP_RX to /5/D/ on RXD
Conditions Min. Typ. Max. Units
10M MII
– 6.5 7 Bit times
Figure 9-10. 10M MII Receive Latency Timing Diagram
TP_RX†
RXCLK
RXD
5
† Manchester encoding
is not shown.
5
t1
5
D
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
127
March, 2004
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