ICS1893BYI-10LF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1893BYI-10LF' PDF : 143 Pages View PDF
ICS1893BY-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.12 MII / 100M Stream Interface: Transmit Latency
Table 9-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
Figure 9-13 shows the timing diagram for the time periods.
Table 9-19. MII / 100M Stream Interface Transmit Latency
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1 TXEN Sampled to MDI Output of First MII mode
Bit of /J/ †
– 2.8 3 Bit times
t2 TXD Sampled to MDI Output of First 100M Stream Interface – 6.1 7 Bit times
Bit of /J/ †
† The IEEE maximum is 18 bit times.
Figure 9-13. MII / 100M Stream Interface Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
Preamble /J/ Preamble /K/
TP_TX†
t1
t2
† Shown
unscrambled.
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
130
March, 2004
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