ICS1893CFILF View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

ICS1893CFILF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Device Technology 

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ICS1893CF Data Sheet - Release

Chapter 9 DC and AC Operating Conditions

9.5.10 100M / MII Media Independent Interface: Transmit Latency

Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time

periods consist of timings of signals on the following pins:

• TXEN

• TXCLK

• TXD (that is, TXD[3:0])

• TP_TX (that is, TP_TXP and TP_TXN)

Figure 9-11 shows the timing diagram for the time periods.

Table 9-17. MII / 100M Stream Interface Transmit Latency

Time

Period

Parameter

Conditions

t1 TXEN Sampled to MDI Output of First MII mode

Bit of /J/ †

Min. Typ. Max. Units

– 2.8 3 Bit times

† The IEEE maximum is 18 bit times.

Figure 9-11. MII / 100M Stream Interface Transmit Latency Timing Diagram

TXEN

TXCLK

TXD

Preamble /J/ Preamble /K/

TP_TX†

t1

† Shown

unscrambled.

ICS1893CF, Rev. J, 08/11/09

Copyright © 2009, Integrated Device Technology, Inc.

All rights reserved.

112

August, 2009

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