ICS1893CFILF View Datasheet(PDF) - Integrated Device Technology
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MFG CO.
'ICS1893CFILF' PDF : 127 Pages View PDF
ICS1893CF Data Sheet Rev. J - Release
Chapter 9 DC and AC Operating Conditions
9.5.13 100M MII Media Independent Interface: Receive Latency
Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
Figure 9-14 shows the timing diagram for the time periods.
Table 9-20. 100M MII / 100M Stream Interface Receive Latency Timing
Time
Period
Parameter
Conditions
t1 First Bit of /J/ into TP_RX to /J/ on RXD 100M MII
Min. Typ. Max. Units
– 16 17 Bit times
Figure 9-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
TP_RX†
RXCLK
RXD
t1
† Shown
unscrambled.
ICS1893CF, Rev. J, 08/11/09
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
115
August, 2009
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