ICS1893CFILF View Datasheet(PDF) - Integrated Device Technology
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Description
MFG CO.
'ICS1893CFILF' PDF : 127 Pages View PDF
ICS1893CF Data Sheet Rev. J - Release
Chapter 9 DC and AC Operating Conditions
9.5.15 Reset: Power-On Reset
Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
Figure 9-16 shows the timing diagram for the time periods.
Table 9-22. Power-On Reset Timing
Time
Period
Parameter
t1 VDD ≥ 2.7 V to Reset Complete
Conditions Min. Typ. Max. Units
–
40 45 500 ms
Figure 9-16. Power-On Reset Timing Diagram
VDD
2.7 V
t1
TXCLK
Valid
ICS1893CF, Rev. J, 08/11/09
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
117
August, 2009
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