ICS1893CY-10LF View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

MFG CO.

ICS1893CY-10LF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

Prev 111 112 113 114 115 116 117 118 119 120 Next

ICS1893CY-10 - Release

Chapter 9 DC and AC Operating Conditions

9.5.3 Timing for Receive Clock (RXCLK) Pins

Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various

interfaces. Figure 9-4 shows the timing diagram for the time periods.

Table 9-10. MII Receive Clock Timing

Time

Period

Parameter

t1 RXCLK Duty Cycle

t2a RXCLK Period

t2b RXCLK Period

t2c RXCLK Period

t2d RXCLK Period

Conditions

Min. Typ. Max. Units

–

35 50 65 %

100M MII (100Base-TX)

– 40 –

ns

10M MII (10Base-T)

– 400 –

ns

100M Symbol Interface (100Base-TX) – 40 –

ns

10M Serial Interface (10Base-T)

– 100 –

ns

Figure 9-4. Receive Clock Timing Diagram

t1

RXCLK

t2

ICS1893CY-10 Rev 1/07

Copyright © 2007, Integrated Device Technology, Inc.

All rights reserved.

121

Share Link: