IR3Y48M View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48M' PDF : 31 Pages View PDF
Other Functions
ADC DIRECT INPUT (ADIN MODE)
Direct input path to ADC or AGC is realized by
register setting. This direct path can be turned off
by register. Black level cancel and clamp are
performed at the same timing of ADCLP low.
IR3Y48M
These controls can be masked by register setting.
BLK, SHR, and SHD controls are ignored at ADIN
mode.
The signal at AGC input is shown below.
ADIN
ADCK
ADCLP
DO0-DO9
(N)
(N+1) (N+2)
(When ADCK is inverted,
signal (N) is sampled by this edge)
Black Cancel & Clamp
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
NOTE : For ADCLP low, both black level cancel and clamp are active at AGC input mode, and only clamp is active at
ADC input mode.
ADIN Signal Processing (AGC Input)
Operation at ADC direct input is shown below.
The zero reference (CLPCAP) is established by
ADCLP pulse. The ADIN input range is from
CLPCAP + 1 V (TYP.) (full scale).
ADIN
Full scale
CLPCAP + 1 V
ADC
dynamic range
= 1 Vp-p
CLPCAP
ADCLP
Clamp ON
ADIN Signal Input Level
STANDBY MODE
The standby mode can be set either by register
setting or STBYN pin.
If one of the above is set, IR3Y48M powers down.
("OR" logic)
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