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ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
MFG CO.
ISPGDX2
Lattice
Lattice Semiconductor Lattice
'ISPGDX2' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
Switching Test Conditions
Figure 23 shows the output test load used for AC testing. Specific values for resistance, capacitance, voltage and
other test conditions are shown in Table 7.
Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V)
VCCO
Device
Output
R1
Test
Point
R2
CL*
*CL includes Test Fixture and Probe Capacitance.
Table 7. Test Fixture Required Components
Test Condition
Default LVCMOS 1.8 I/O (L -> H, H -> L)
R1
R2
CL
106 106 35pF
Timing Ref.
VCCO/2
LVCMOS3.3 = 1.5V
LVCMOS I/O (L -> H, H -> L)
35pF LVCMOS2.5 = VCCO/2
LVCMOS1.8 = VCCO/2
Default LVCMOS 1.8 I/O (Z -> H)
106 35pF
VCCO/2
Default LVCMOS 1.8 I/O (Z -> L)
106
— 35pF
VCCO/2
Default LVCMOS 1.8 I/O (H -> Z)
106 5pF
VOH - 0.15
Default LVCMOS 1.8 I/O (L -> Z)
106
5pF
VOL + 0.15
Note: Output test conditions for all other interfaces are determined by the respective standards.
VCCO
1.8V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = 2.3V
LVCMOS1.8 = 1.65V
1.65V
1.65V
1.65V
1.65V
49
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