P30-65nm SBC
Figure 7: QUAD+ SCSP Ballout and Signals (128-Mbit)
Pin 1
1
2
3
4
5
6
7
8
A
DU
DU
Depop Depop Depop Depop
DU
DU
A
B
A4
A18
A19
VSS
VCC
VCC
A21
A11
B
C
A5
RFU
RFU
VSS
RFU
CLK
A22
A12
C
D
A3
A17
RFU
VPP
RFU
RFU
A9
A13
D
E
A2
A7
RFU
WP#
ADV#
A20
A10
A15
E
F
A1
A6
RFU
RST#
WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT F2-CE#
G
H
RFU
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
RFU F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
RFU
RFU
RFU
RFU
VCC
VCCQ
RFU
K
L
VSS
VSS
VCCQ
VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
Depop Depop Depop Depop
DU
DU
M
1
Legends:
2
3
4
5
6
Top View - Ball Side Down
De-Populated Ball
Reserved for Future Use
Do Not Use
7
8
Control Signals
Address
Data
Power/Ground
Notes:
1.
A22 is valid for 128-Mbit densities; otherwise, it is a no connect (NC).
2.
A21 is valid for 64-Mbit densities and above; otherwise, it is a no connect (NC).
3.
F2-CE# and F2-OE# are no connect (NC) for all densities.
4.
Unlike TSOP and Easy BGA, A0 is the least significant address bit for the QUAD+ package. Unless otherwise indicated, for
the purpose of brevity, this document will consolidate all later discussions to A1 as the least significant Address bit.
Datasheet
13
Apr 2010
Order Number:208033-02