JS28F128P30BF65A View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
JS28F128P30BF65A
Numonyx -> Micron
'JS28F128P30BF65A' PDF : 90 Pages View PDF
P30-65nm SBC
5.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
Bus cycles to/from the P30-65nm SBC device conform to standard microprocessor bus
operations. Table 5, “Bus Operations Summary” summarizes the bus operations and
the logic levels that must be applied to the device control signal inputs.
Table 5: Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
VIH
X
L
L
Read
L
H
Deasserted Output
2
Synchronous
VIH
Running
L
L
L
H
Driven
Output
-
Write
VIH
X
L
L
H
L
High-Z
Input
1,2
Output Disable
VIH
X
X
L
H
H
High-Z
High-Z
2
Standby
VIH
X
X
H
X
X
High-Z
High-Z
2
Reset
VIL
X
X
X
X
X
High-Z
High-Z
2,3
Notes:
1.
Refer to the Table 7, “Command Bus Cycles” on page 21 for valid DQ[15:0] during a write
operation.
2.
X = Don’t Care (H or L).
3.
RST# must be at VSS ± 0.2V to meet the maximum specified power-down current.
5.1
Read - Asynchronous Mode
To perform an asynchronous page or single word read, an address is driven onto the
address bus, and CE# is asserted. ADV# can be driven high to latch the address, or it
must be held low throughout the read cycle. WE# and RST# must already have been
deasserted. WAIT is set to a deasserted state during asynchronous page mode and
single word mode as determined by RCR.10. CLK is not used for asynchronous page-
mode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]
after an initial access time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications”
on page 50).
Note:
If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level,
WAIT signal can be floated and ADV# must be tied to ground.
In asynchronous page mode, eight data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest three address bits determine which word of the
8-word page is output from the data buffer at any given time.
Refer to the following waveforms for more detailed information:Figure 19,
“Asynchronous Single-Word Read (ADV# Low)” on page 51, and Figure 20,
“Asynchronous Single-Word Read (ADV# Latch)” on page 52, and Figure 21,
“Asynchronous Page-Mode Read Timing” on page 52.
5.2
Read - Synchronous Mode
To perform a synchronous burst read on array or non-array, an initial address is driven
onto the address bus, and CE# is asserted. WE# and RST# must already have been
deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately,
Datasheet
16
Apr 2010
Order Number: 208033-02
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