KB2516 View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'KB2516' PDF : 30 Pages View PDF
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Output mode
Single channel output mode
Dual channel interleaving output mode
Dual channel parallel output mode
ADC_CK
Channel A
Channel B
D0 D1 D2 D3 D4 D5
HZ
Channel A
Channel B
D0
D2
D4
D1
D3
D5
Channel A
Channel B
D0
D2
D4
D1
D3
D5
• ADC clock output control (ADCK_ENB)
ADCK_ENB = 0: Output clock is enabled
ADCK_ENB = 1: Output clock is disabled (HZ)
• ADC clock output inverting control (ADCK_INV)
ADCK_INV = 0: Default ADC_CK and ADC_CKB output
ADCK_INV = 1: Inverted ADC_CK and ADC_CKB output
• ADC clock selection control (ADCK_SEL)
ADCK_SEL = 0: Internal PLL output is used
ADCK_SEL = 1: External clock (ADC_CKEX) is used
• ADC output buffer state control (ADOM)
ADOM<1:0>
00
01
10
11
Output Buffer State
Normal output mode
01010101
10101010
High impedance
Phase-Locked loop (PLL) Control
• VCO free running frequency control (IFRSH)
IFRSH<1:0>
00
01
10
11
Free Running Frequency
Default VCO max. freq.
Increase VCO max. freq. 7.5%
Increase VCO max. freq. 15%
Increase VCO max. freq. 30%
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