KB2516 View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'KB2516' PDF : 30 Pages View PDF
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
COAST
HSYNCO
VSYNCO
td5
td6
tVS_DELAY
tVS_LENGTH
tVS_DELAY : COAST rising edge to VSYNCO rising edge delay
tVS_LENGTH : VSYNCO signal length (high duration)
td5
: HSYNCO rising edge to VSYNCO rising edge delay
td6
: HSYNCO rising edge to VSYNCO falling edge delay
Fig7. VSYNCO Output Timing Diagram
• VSYNCO signal delay control (VSD)
tVS_DELAY = VSD × DIV × T - td5, VSD ≥ 0
• VSYNCO signal length control (VSL)
tVS_LENGTH = VSL × DIV × T - td5 + td6, VSL ≥ 1
• PLL output clock enable (CKA_ENB, CKB_ENB, CKC_ENB)
0: Output is enabled
1: Output is disabled (low output)
• PLL output clock inverting control (CKA_INV, CKB_INV, CKC_INV)
0: Non-inverted clock output
1: Inverted clock output
• PLL VI converter gain control (VI_GAIN)
0: 375 uA/V
1: 470 uA/V
KB2516 (Preliminary)
25
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