TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
All supply pins have to be decoupled, with two capacitors:
one for high frequencies (approximately 1nF) and one for the low frequencies (approximately 100nF or higher).
PLL loop filter (C1, C2, R1)
fn
=
1
2π
KO I P
(C1 + C2 ) N
where :
f n = the natural PLL frequency
KO = the VCO gain
N = the division number
C1andC2 = capacitors of the PLL filter
fZ
=
2π
×
1
R1 × C1
and ξ = 1 × fn
2 fZ
where :
f Z = loop filter zero frequency
R1 = the choosen resistance for the filter
ξ = the damping factor
C1, C2, and R1 values are selected to satisfy the following conditions.
f n f ref ≅ 0.05
ξ ≅ 1.5
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