KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED)
Pin
Number
86
87
88
89
90
91
92
93
94
Pin
Name
SCONF1
SCONF0
GNDD
VDDC
LED5-2
LED5-1
LED5-0
LED4-2
LED4-1
Type,
Note
2-1
IPD
IPD
GND
P
IPU/O
IPU/O
IPU/O
IPU/O
IPU/O
Port
—
—
—
—
5
5
5
4
4
Pin Function, Note 2-2
Pins 91, 86, and 87 are dual MII/RMII configuration pins for the Port
5 MAC5 MII/RMII and PHY [5] MII/RMII. SW5-MII supports both
MAC mode and PHY modes. P5-MII supports PHY mode only. See
pins configuration below:
Pin# (91, 86, 87)
Port 5 Switch
MAC5 SW5- MII/
RMII
Port5 PHY5
P5- MII/RMII
000
Disable, Otri
Disable, Otri
001
PHY Mode MII, or
RMII
Disable, Otri
010
MAC Mode MII, or
RMII
Disable, Otri
011
PHY Mode SNI
Disable, Otri
100
Disable (default)
Disable (default)
101
PHY Mode MII or
RMII
P5-MII/RMII
110
MAC Mode MII or
RMII
P5-MII/RMII
111
PHY Mode SNI
P5-MII/RMII
Dual MII/RMII configuration pin. See Pin 86 descriptions.
Digital ground.
1.2V digital core VDD.
LED indicator 2.
Strap option:
Aging setup. See “Aging” section.
PU (default) = aging enable
PD = aging disable.
LED indicator 1.
Strap option:
PU (default): enable PHY [5] MII I/F.
PD: tri-state all PHY [5] MII output. See “Pin 86 SCONF1.”
LED indicator 0.
Strap option for port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negotiation. Strap to Register76 bit [7].
LED indicator 2
LED indicator 1
2016 Microchip Technology Inc.
DS00002246A-page 13
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