KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
3.0 FUNCTIONAL DESCRIPTION
The KSZ8895MQX/RQX/FQX/MLX contains five 10/100 physical layer transceivers and five media access control
(MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-
port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this
mode, access to the fifth MAC is provided through a media independent interface (MII/RMII). This is useful for imple-
menting an integrated broadband router. The third mode uses the dual MII/RMII feature to recover the use of the fifth
PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the
P5-MII/RMII port.
The KSZ8895MQX/RQX/FQX/MLX has the flexibility to reside in a managed or unmanaged design. In a managed
design, a host processor has complete control of the KSZ8895MQX/RQX/FQX/MLX via the SPI bus, or the MDC/MDIO
interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MQX/RQX/FQX/MLX supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper
ports with Auto MDI/MDIX. The KSZ8895FQX supports 100BASE-FX on port 4, and port 3 is configurable either copper
as default or fiber. The KSZ8895MQX/RQX/FQX/MLX can be used as a fully managed five-port switch or hooked up to
a microprocessor by its SW-MII/RMII interfaces for any application solutions.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP tech-
nology that make the design more efficient and allows for reduced power consumption and strong electrical noise immu-
nity.
Major enhancements from the KS8995MQ/RQ/FMQ to the KSZ8895MQX/RQX/FQX include more saving power, there
is no a limitation for the center taps of the transformer in KSZ8895MQX/RQX/FQX, KSZ8895MQ/RQ/FMQ request the
center taps of RX an TX of the transformer not to be tied together for saving power, except using 0.11 µm process and
add Microchip LinkMD feature in KSZ8895MQX/RQX/FQX switches. The KSZ8895MQX/RQX/FQX are complete com-
patible with KSZ8895MQ/RQ/FMQ.
3.1 Physical Layer Transceiver
3.1.1 100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-
version, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII
data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding
followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in
MLT3 current output. The output current is set by an external 1% 12.4 kΩ resistor for the 1:1 transformer ratio. It has a
typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and
timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
3.1.2 100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiv-
ing side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair cable.
Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its char-
acteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and can self-adjust against environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the
4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.1.3 PLL CLOCK SYNTHESIZER
The KSZ8895MQX/RQX/FQX/MLX generates 125 MHz, 83 MHz, 41 MHz, 25 MHz, and 10 MHz clocks for system tim-
ing. Internal clocks are generated from an external 25 MHz crystal or oscillator.
DS00002246A-page 20
2016 Microchip Technology Inc.
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