L6238 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6238' PDF : 35 Pages View PDF
Figure 17: Charge Pump Circuit.
L6238
lower drivers in a brake mode if the analog supply
is lost.
Figure 17 is a simplified schematic of the charge
pump circuitry. A capacitor, Cpump, is used to re-
trieve energy from the analog supply and then
”pumps” it into the storage capacitor, Cresvr. An in-
ternal 300kHz oscillator first turns ON Q2 to
quickly charge Cpump to approximately the rail
voltage. The oscillator then turns ON Ql while
turning OFF Q2. Since the bottom plate of Cpump
is now effectively at the rail potential, Cresvr is
charged to ~ twice the rail voltage via D2. A zener
referenced series-pass regulator supplies a volt-
age, Vbrake, during brake mode.
5.4 Output Current Control
The output current is controlled in a linear fashion
via a transconductance loop. Referring to figure
18, the sourcing FET of one phase is forced into
full conduction by connecting the gate to Vpump,
while the sinking transistor of an appropriate
phase operates as a transconductance element.
To understand the current control loop, it will be
assumed that Q2 in figure 18 is enabled via SW2
by the sequencer.
During a run condition, the current in Q2 is moni-
tored by a resistor R4 connected to the Rsense in-
put. The resulting voltage that appears across R4
is amplified by a factor of four by A3 and is sent to
A2 where it is compared to the PLL error signal.
A2 provides sufficient drive to Q2 in order to
maintain the motor speed at the proper level as
commanded by the PLL.
During initial start-up, the error signal from the
output of the PLL Phase/Frequency Detector will
be at compliance in order to quickly bring the mo-
tor up to correct speed. The motor current during
this condition can be safely limited to a predeter-
mined value by applying a voltage to the ILIM
SET input.
The voltage at this input is buffered by A1 and
sent to multiplexer, SWl. The output voltage of the
multiplexer, Vclmp, is used to control the maxi-
mum non-inverting input voltage for amplifier A2.
This multiplexer also receives a voltage that is 1/2
the ILIM SET value via a resistor divider con-
nected to the buffer. Control bit llim Gain deter-
mines which voltage is available at the output of
the multiplexer and allows a 2:1 change in the
output current limit under software control.
For example, if the Ilim Gain control bit is set
high, and 3.3V were applied to the ILIM SET in-
put, then Vclmp would equal 1.65V. Since A3 has
a voltage gain of 4, this would translate to a maxi-
mum sensed voltage at the Rsense input equal to
0.41V. If Rslew were selected to be 0.33 Ω, then
the maximum output current would be limited to
~1.25A.
By setting the Ilim Gain control bit low, Vclmp now
equals ILIM SET, and the clamped sensed volt-
age at the Rsense input would be doubled to
0.82V, allowing a maximum of 2.5A at the output.
21/35
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