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L6238 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
L6238
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'L6238' PDF : 35 Pages View PDF
actually exceeded the mask period and was de-
tected as a zero crossing. This resulted in im-
proper sequencing of the outputs relative to the
proper phases and caused the motor to spin
down.
If the application requires a slow rate of slew at
the output, an external network can be connected
as shown in figure 25. A resistor, Rl is selected to
achieve the desired slew rate when the system is
in phase lock. A second resistor, R2, in series
with a diode, Dl, is connected between the SLEW
RATE pin, and the LOCK output. At start up, the
LOCK output is low, and R2 is in parallel with Rl
resulting is a faster slew rate. When lock is
achieve, the LOCK output is high, and R2 is es-
sentially disconnected from the circuit.
5.7 Ext PFET Driver
The power handling capabilities of the 3 phase
output stage can be extended with the addition of
a single P-Channel FET.
Figure 26 shows the Ext FET connection and
demonstrates how the L6238 automatically
senses the FETs presence. When the voltage at
the Gate Drive pin is 0.7V, the output of com-
parator A3 goes high, removing the variable drive
Al from the internal FETs and connects them in-
stead to Vanalog via the commutation switches to
facilitate full conduction. The upper FETs drive
Figure 26: External P-Fet.
Figure 25: Dual Slew Rate.
L6238
paths are not shown for clarity. A3 also closes
SW2 allowing Al to linearly drive the external P-
Channel FET Ql via inverter A2.
5.8 Bemf Sensing
Since no Hall Effect Sensors are required, the
commutation information is derived from the Bemf
voltage zero-crossings of the undriven phase with
respect to the center tap. The Bemf comparator
and associated signal levels are depicted in figure
27. For reliable operation, the Bemf signal ampli-
tude should be a minimum of ± 60 mV to be prop-
erly detected. In order to provide for noise immu-
nity, internal hysteresis is incorporated in the
detection circuitry to prevent false zero crossing
detection.
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