L6238 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6238' PDF : 35 Pages View PDF
L6238
Table 5 lists the 16 available control bits along
with a description and power up default values.
Certain bits are replications of their external pin
counterparts while others provide the means to
”customize” the controller to match a unique ap-
plication and are described in further detail below.
Phase Delay - A more efficient torque profile
can be achieved by advancing the commuta-
tion angle to compensate for the L/R time con-
stant. There are 3 bits in the serial port that are
used to program the delay between the zero-
crossing and the commutation point. Thus the
user has the ability to use the motor more effi-
ciently by programming the optimal delay. Ta-
ble 6 is a mapping between the serial ports bits
and the commutation delay.
In selecting the phase delay, the amount of
slew rate introduced must be considered, since
the switching is effectively at the 50% points
and this delay can be a significant contribution.
Lock Threshold - Bits 2 and 3 control the
phase error window between the reference
and the motor that must be met in order to al-
low the LOCK signal to go high. Four differenct
Figure 34: Failed Rysync.
thresholds cover the range between 6.4 and
51.2 us as shown in Table 7.
Auto Start Delay - Table 8 lists the delays
available for the Align & Go start up algorithm
with values for 90Hz and 60Hz applications.
6.6 Status Register
The serial port also contains 16 bits that give use-
ful information about the inner workings of the
controller. Table 9 provides a functional descrip-
tion of each of the status bits. The status bits
prove valuable during certain situations with one
example highlited below.
Align +Go - These 2 bits can be used to deter-
mine if a resync operation was succesful or
not. During a commanded resync, these bits
will be initially high, and will stay high if the
resync was successful. However, figure 34
shows the timing of these 2 bits during an un-
succesful resync where the Go bit goes low
419 ms after the resync command if no Bemf
zero crossing is detected.
Tasd <1>
0
0
1
1
Tasd <0>
0
1
0
1
Note: PLL Reference Frequency = 90Hz
System Clock = 10MHz.
Ta
0.178 s
0.256 s
0.533 s
0.711 s
Tg
0.711 s
1.422 s
2.133 s
2.844 s
Ts
0.419 s
0.419 s
0.419 s
0.419 s
30/35
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