L6245 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6245' PDF : 15 Pages View PDF
REGISTER DEFINITION and 3bit Address Code
Table 1: Status Register (A.C. 001)
Bit
Name
7 NC
6 NC
5 NC
4 NC
3 REVERSE SPIN
2 OVER TEMP.
1 SPIN SENSE
0 OVER VEL SET
POR Initial
Value
1
1
0
1
L6245
Table 5: Spin D/A Register (A.C. 101)
Bit
Name
7 Most Significant Bit
6
5
4
3
2
1
0 Least Significant Bit
POR Initial
Value
0
0
0
0
0
0
0
0
Table 2: VCM Driver Register (A.C. 010)
Bit
Name
7 NC
6 NC
5 NC
4 UNLOAD HD
3 LOAD HD
2 ENABLE ISENSE
1 HIGH GAIN VCM
0 ENABLE VCM
POR Initial
Value
0
0
0
0
0
Table 6: Interrupt Mask Register (A.C. 110)
Bit
Name
POR Initial
Value
7 NC
6 NC
5 NC
4 NC
3 NC
2 MASK REV Spin
0
1 MASK OVER TEMP ERROR
0
0 MASK OVER VEL ERROR
0
Table 3: Spin Control Register (A.C. 011)
Bit
Name
7 NC
6 LINEAR/PWM
5 INCREMENT STATE
4 RESET STATE
3 RUN/SEARCH
2 UNI/BI
1 HIGH GAIN SPIN
0 ENABLE Spin
POR Initial
Value
0
0
0
0
0
0
0
0
Table 4: VCM D/A Register (A.C. 100)
Bit
Name
7 Most Significant Bit
6
5
4
3
2
1
0 Least Significant Bit
POR Initial
Value
0
0
0
0
0
0
0
0
Table 7: Phase Delay Register (A.C. 111)
Bit
Name
7 NC
6 NC
5 NC
4 NC
3 Most Significant Bit
2
1
0 Least Significant Bit
POR Initial
Value
0
0
0
0
SYSTEM BUS DESCRIPTION
The system bus is designed as a data acknow-
ledge handshanking bus. At the beginning of the
bus cycle the address and chip select are de-
coded transparently and qualified with read or
write going low. On a read operation, data must
not be driven for 5nsec after read goes low to al-
low the bus to clear. Once data is driven, data ac-
knowledge is driven low to notify the processor
that data is on the bus and ready to be read. The
processor reads the data and responds by raising
read. This is an indication that the processor has
compleated the read and cycle is complete. Data
acknowledge and data must go to high im-
pedence within 20ns to clear the bus for the next
11/15
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