L6245 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6245' PDF : 15 Pages View PDF
L6245
cycle. On a write operation, following write going
low and whatever setup time required to latch
data, data acknwledge is driven low. This notifies
the processor that the cycle can end. This proces-
sor responds by raising write, indicating the end
of the cycle. Data acknowledge must go to high
impedance within 20nsec to clear the bus for the
next cycle.
This handshaking design allows a peripheral to
control the length of the bus cycle. The peripheral
Figure 1: System Bus Timing (see Table 8)
can take as much time as it needs to drive data
onto the bus, then drive DTACK low. Likewise,
the peripheral can wait as long as it needs to set
up data and latch it (or set up data if WR is used
to latch), then drive DTACK low. However, per-
formance is an issue, so even though this control
has been given to the peripheral, it must not be
abused. All delays are minimized to assure opti-
mum system speed, infact the bus can be driven
synchronously (E.G. has regarding DTACK) when
procesor clocks below 12MHz are used.
Table 8: System Bus Timing
Symbol
TAS
TCS
TASW
TASRD
TRDDV
TRDDH
TRDCS
TDVDT
TDTRD
TRDDT
TASWR
TDVWR
TWRDTL
TDTWR
TWRCS
TWRDT
TWRDH
Description
Address Setup Time (non MUX bus; (MUX bus)
System Select to Address Strobe
Address Strobe Width
Address Strobe to RD
RD to Data Driven
Read Data Hold
RD High to CS High
Data Valid to DTACK
DTACK to RD High
RD High to DTACH High
Address Strobe to WR
Write Data Valid to WR
WR to DTACK
DTACK to WR High
WR High to CS High
WR High to DTACK High
Write Data Hold
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