L6256 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6256' PDF : 28 Pages View PDF
L6256
Test conditions for serial port timing spec:
Parameter
Tr, Tf
Vdh
Vdl
Vch
From/To
SCLK rise, fall
Min.
2.4
2.4
Max.
5
0.8
Note: The serial port must meet these specifications up to the thermal shutdown temperature.
Figure 7. Serial Port Read Timing Waveforms
Units
ns
V
V
V
Figure 8. Serial Port Write Timing Waveforms
Table of Address Values
S0, S1, S2 always 1 - any other value indicates a
packet for use by another chip.
S2 may be used only as part of the VCM register
address, as ATT_EN.
Register
VCM DAC
Aux Control Register
VCM Control Register
Commutation Preload
Register (CPR)
Test Register (*)
Status Register
A0-3
11xx
0111
0001
0011
1000
0100
R/W
Write Only
R/W
R/W
Write Only
R/W
Read only
(*) represents revised specification.The test register is now imple-
mented in both chips
14/28
REGISTER BIT DEFINITIONS
All bits in the control registers are asserted (true)
when positive. The appropriate status bit answers
to the same address and bit location as the wri-
table bit which causes the action.
This means that when a read is performed, the
actual value read back is not just an echo from
the write register, but represents the status of the
function requested. In most cases this is a direct,
unlatched output from internal circuitry.
Most status bits are reset after being read once.
The control registers have control bits as follows:
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